This invention relates to tristate transistor-transistor logic (TTL) circuits and more particularly to reducing power dissipation in such circuits when the circuits are in the high impedance third state.
Tristate TTL circuits, which can assume a high impedance third state as well as the binary "1" and "0" states, are known in the art. Such circuits are most commonly used in applications in which a plurality of circuits are coupled to a common bus, and only one of the circuits provides data (a binary "1" or "0") to the bus at a time while the other circuits are in the high impedance third state.
A conventional tristate TTL circuit is shown in FIG. 1. The circuit 100 includes a logic gate 101 having a data input terminal 101 for receiving a data signal, an output terminal 102, a first power supply terminal 104 for receiving a V.sub.CC supply voltage (typically 5 V) and a second power supply terminal 105 for receiving a second power supply voltage, which in this case is ground. Connected between the output terminal and the V.sub.CC supply terminal is a "pullup" network consisting of transistors T4 and T5 connected as a modified Darlington pair, a resistor R6 connected between the V.sub.CC supply terminal and the common collectors of T4 and T5, a resistor R5 and a diode D3 connected in series between the emitter of T4 and the output terminal. When T4 and T5 are driven to their conducting states, the pullup network is activated to "source" current from the V.sub.CC supply terminal to the output terminal. Connected between the output terminal and the ground terminal is a "pulldown" network consisting of a transistor T1. When T1 is driven to its conducting state, the pulldown network is activated to "sink" load current from the output terminal to the ground terminal. The pullup and pulldown networks are selectively activated by a phase splitter network consisting of a phase splitter transistor T2 having its base connected to the data input terminal and its collector and emitter respectively connected to the bases of T4 and T1, a collector resistor R1 connected between the collectors of T2 and the V.sub.CC supply terminal, and a conventional squaring network, consisting of a transistor T3 and resistors R3 and R4, connected between the emitter of T2 and the ground terminal. A resistor R2 is connected between the base of T2 and the V.sub.CC supply terminal.
When the data signal received by the base of T2 is at a low level such that T2 is in the nonconducting state, the base of T4 is pulled to approximately V.sub.CC through R1 causing T4 and T5 to go to the conducting state, and base current to T1 is removed causing T1 to go to the nonconducting state. Under these conditions, the pullup network is active, and the pulldown network is inactive causing the output terminal to go to a logic "1" voltage level of greater than 2.5 V (assuming positive logic).
When the data signal is a high level such that T2 is driven to the conducting state by base current provided through R2, the base of T4 is pulled to a low voltage causing T4 and T5 to go to the nonconducting state, and T1 is driven to the conducting state by base current provided by T2. Under these conditions, the pullup network is inactive, and the pulldown network is active causing the output terminal to go to a logic "0" level of less than 0.4 V (assuming positive logic).
The circuit of FIG. 1 also includes a disabling network 106 consisting of a control input terminal 103 and a transistor T11 having its base connected to receive a control signal from the control input terminal, its collector connected to the cathodes of coupling diodes D1 and D2 and its emitter connected to the ground terminal. The anodes of D1 and D2 are connected to the base and collector of T2, respectively.
When the control signal is a low level such that T11 is in the nonconducting state, the disabling network is inactive and has virtually no effect on the bistate operation of the gate described above. However, when the control signal is at a high level such that T11 is driven to the conducting state, the disabling circuit is active to sink current from the bases of T2 and T4 causing T1, T2, T4 and T5 to all go to the nonconducting state. Under these conditions the pullup and pulldown networks are both inactive, regardless of the data signal, and the output terminal goes to a third state of being isolated from the V.sub.CC and ground terminals by the nonconducting-state impedances of T5 and T1, respectively.
The diodes D1 and D2 coupling the gate to the disabling network permit only one-way current flow from the gate to the disabling network. Therefore, more than one gate may be coupled through similar diodes to the disabling network.
In order to achieve higher switching speeds for the circuit of FIG. 1, typically transistors T1, T2, and T3 of the gate and T11 of the disabling network are Schottky-clamped, and diodes D1, D2 and D3 of the gate are Schottky diodes. It is well known that a Schottky-clamped transistor has a shorter turn-off time than a conventional transistor, and a Schottky diode has a shorter charge storage time than a conventional diode. In addition, the resistors R1, R2, R5 and R6 of the gate have relatively low values to provide high internal drive currents for the transistors of the gate. For example, typical values of R1, R2, R5 and R6 in the circuit of FIG. 1 are 900.OMEGA., 2.8 K.OMEGA., 400.OMEGA. and 60.OMEGA., respectively.
One problem with the conventional tristate TTL circuit is that when the disabling network is active, a relatively low impedance current path exists between the V.sub.CC supply terminal and the ground terminal through R1, D2 and T11. Consequently, the circuit has a relatively high power dissipation when it is in the high impedance state. For example, the circuit of FIG. 1 typically dissipates 7.5 mW in the logic "1" state, 27.5 mW in the logic "0" state and 30 mW in the high impedance state. In the common bus application described above, all but one of the circuits coupled to a bus are in the high impedance state at any given time. Therefore, the high impedance state power dissipation of conventional tristate logic circuits can contribute substantially to the overall power dissipation of a heavily bus-oriented system, such as a data processor. It is generally desirable to minimize the power dissipation of a system in order to minimize system cost with respect to power supply, cooling and space requirements.
Another problem with the conventional tristate TTL circuit related to the problem of high power dissipation is that the disabling network must sink a relatively large current for each gate it serves. Consequently, a typical disabling network having a current sinking capability of 20 mA can serve only three gates of the type shown in FIG. 1. Consequently, a system using many tristate logic gates may require an excessive number of disabling networks. Where the system is wholly or partially integrated on a single chip, it is particularly important to minimize the number of disabling networks needed by the system in order to minimize chip area usage.
The high impedance state power dissipation of a tristate TTL circuit can be reduced by raising the value of the collector resistor R1 to increase the impedance of the current path to the disabling network. However, raising the value of R1 has the disadvantage of also reducing the current drive to the pullup and pulldown networks during bistate operation and, therefore, degrades the switching speed of the circuit in both the logic "1" to logic "0" (1-0) and the logic "0" to logic "1" (0-1) transitions.
A prior art circuit technique for reducing the high impedance state power dissipation of a tristate TTL circuit which causes less degradation in the switching speed of the circuit is to raise the value of the collector resistor and to add a current boosting transistor connected in parallel with the phase splitter transistor. The current boosting transistor has its base and emitter connected to the base and emitter of the phase splitter transistor T2, respectively. The collector of the current boosting transistor is connected either directly to the V.sub.CC supply terminal or indirectly through a relatively low valued resistor. Thus, the high impedance power dissipation is reduced by the higher value of the collector resistor which increases the impedance of the current path to the disabling network, and additional current drive to the pulldown network is provided by the current boosting transistor, which is not coupled to the disablings network. Therefore, this prior art technique reduces the high impedance state power dissipation while substantially preserving the switching speed of the 1-0 transition, as compared to that of the conventional TTL circuit.
However, this technique has the disadvantage in that the current drive to the pullup network is not boosted, and the circuit suffers from a degradation in the switching speed of the 0-1 transition owing to the relatively high value of the collector resistor.
Therefore, a need exists for a tristate TTL circuit having lower power dissipation in the high impedance state than the prior art while substantially preserving the switching speeds of both the 0-1 and the 1-0 transitions as compared to those of the conventional tristate TTL circuit.